As semiconductor technology progresses, shrinking device dimensions has become an increasingly complex task. One approach to overcome these difficulties is the vertical integration of multiple semiconductor chips, allowing either larger number of devices per unit (e.g. in memory applications) or the integration of chips providing different functionality, allowing better performance of a hybrid system (e.g. sensor, processor and memory). One method for vertical integration is based on Through Silicon Via (TSV), in which conducting pillars are formed within the silicon substrate, to be later used for contacting successive chips. TSV technology provides the electrical interconnect between the components in different layers, and also provides mechanical support. In TSV technology, a via is fabricated in a silicon chip with different active integrated circuit devices or other devices fabricated by a semiconductor process, and the via is filled with metal such as Cu, Au, W, solders, or a highly-doped semiconductor material such as polysilicon. Multiple components provided with such vias are then stacked and bonded together.
One critical step in the TSV process is the via formation, in which a pattern of contacts is etched into the silicon. In this process, defects in the TSV might be produced. In order to maintain the required via quality, it is essential to detect defective vias.
In WO 2014/006614, assigned to the assignee of the present invention, a method and system were presented for use in inspection of via containing structures. According to this technique, measured data indicative of a spectral response of a via-containing region of a structure under measurements is processed, and, upon identifying a change in at least one parameter of the spectral response with respect to a spectral signature of the via-containing region, output data is generated indicative of a possible defect at an inner surface of the via.